1. Field of the Invention
The present invention relates to an intermediate potential generating circuit having an output stabilizing circuit for generating an intermediate potential.
2. Description of the Related Art
In a semiconductor integrated circuit, a potential having an intermediate value between a power source voltage and a ground voltage must be frequently generated. As an intermediate potential generating circuit for generating the intermediate potential, for example, a conventional circuit described in U.S. Pat. No. 4,663,584 is well known.
The conventional intermediate potential generating circuit, as shown in FIG. 1, is constituted by a bias potential generating circuit 10 and a driving circuit 20. In the bias potential generating circuit 10, a resistor R1, a diode-connected n-channel MOS transistor Q1 whose gate and drain are short-circuited, a diode-connected p-channel MOS transistor Q2 whose gate and drain are short-circuited, and a resistor R2 are arranged in series in this order between a voltage supply source Vcc on a high potential side and a voltage supply source Vss on a ground potential side. A reference voltage Vs depending on a resistance ratio of the resistor R1 to the resistor R2 can be obtained at a series-connection point between the MOS transistors Q1 and Q2. A bias voltage Vb1 which is higher than the reference voltage Vs by the threshold voltage of the n-channel MOS transistor Q1 is obtained at a series-connection point between the resistor R1 and the n-channel MOS transistor Q1, and a bias voltage Vb2 which is lower than the reference voltage Vs by the threshold voltage of the p-channel MOS transistor Q2 is obtained at a series-connection point between the resistor R2 and the p-channel MOS transistor Q2. The bias voltages Vb1 and Vb2 are both applied to the driving circuit 20.
The driving circuit 20 is constituted by a source-follower n-channel MOS transistor Q3 and a source-follower p-channel MOS transistor Q4. The n-channel MOS transistor Q3 has a drain connected to the voltage supply source Vcc and a source connected to an output node 30 for obtaining an output potential Vo. The p-channel MOS transistor Q4 has a drain connected to the voltage supply source Vss and a source connected to the output node 30. The bias voltages Vb1 and Vb2 obtained by the bias potential generating circuit 10 are applied to the gates of the MOS transistors Q3 and Q4, respectively.
In FIG. 1, reference symbol C denotes a parasitic capacitor, and reference numeral 40 denotes a load circuit, driven by the driving circuit 20, for forming an inverter circuit obtained by series-connecting a p-channel MOS transistor Q7 and an n-channel MOS transistor Q8.
The intermediate potential generating circuit has a preferable load drivability and low current consumption characteristics in a non-load state. The driving circuit 20 is constituted by the source-follower MOS transistors Q3 and Q4. As a result, when the value of a load current flowing in the load circuit 40 connected to the output node 30 is increased, a variation in the output potential Vo is undesirably increased with respect to the set reference voltage Vs.
when the load drivability of the MOS transistors Q3 and Q4 in the driving circuit 20 is increased to suppress variation in the output voltage Vo caused by the load current flowing in the load circuit 40, a difference between each of the bias voltages Vb1 and Vb2 and the reference potential Vs is essentially higher than each of the threshold voltages of the MOS transistors Q3 and Q4. Therefore, a through current undesirably flows between the voltage supply sources Vcc and Vss in the driving circuit 20 in a non-load state.
Thus, in the conventional intermediate potential generating circuit, as the load current is increased, variation in output potential is undesirably increased. However, even if this drawback were eliminated, current consumption in a non-load state would be increased.